The Free Silicon Conference is a yearly event taking place in Paris Sorbonne University. The event is dedicated to Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. There, experts and enthusiasts are able to discuss various part of the strategy and process of creation of Free Silicon. The goal of the conference is simple, make the technology behind integrated circuits accessible to small businesses, startups, universities, and schools with its motto: "Education, sustainability and innovation by openness and collaboration!"
The conference is done with the funding of the Go IT! Horizon project. To learn more about the subject, past panels and presentations can be found on the peertube channel of the event.
Registration can be done by email, the event is free of charge.
References
Contact email
Details
Agenda
As of 4 July:
July 10, Monday (Day 1)
- 9:00-9:30, Registration and coffee
Welcome
- 9:30-9:45, Welcome from the LIP6
- 9:45-9:55, Welcome from the Free Silicon Foundation
Keynote speech
- 10:00-10:30, Lukas Hartmann (MNT Research), The road to fully open hardware mobile computing
High-level design and logic-synthesis
- 10:30-11:00, Martin Schoeberl (DTU Compute), Software-Defined Hardware: Digital Design in the 21st Century with Chisel
- 11:00-11:30, Charles Papon (SpinalHDL), A progressive introduction to memory bus interconnect API in Software-Defined Hardware
- 11:30-12:00, Loïc Sylvestre (Macle), Mixing software abstractions for high-level FPGA programming
- 12:00-13:30, lunch break
- 13:30-14:00, Tristan Gingold (GHDL), Toward multi-language open-source HDL simulation
- 14:00-14:30, N. Engelhardt (YosysHQ GmbH), Recent Developments from YosysHQ
- 14:30-15:00, Benjamin Barzen (ABC), Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?
- 15:00-15:30, Thomas Benz (ETH Zurich), Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana
Foundries and PDKs
- 15:30-16:00, Staf Verhaegen (Chips4Makers), Proof-of-concept for scalable analog blocks using the PDKMaster framework
- 16:00-16:30, Afternoon break. Coffee is served on-campus
- 16:30-17:00, Rene Scholz and Sergei Andreev (IHP Microelectronics), Open source Design Flow status and roadmap for IHP BiCMOS technology
On-going FOS silicon projects
- 17:00-17:30, Matthew Venn (YosysHQ, ChipFlow), TinyTapeout - what happened and next steps
- 17:30-18:00, Thomas Parry (SPHERICAL), Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
Sustainability (part 1)
- 18:00-18:45, David Bol (ICTEAM Institute, UC Louvain), Analyzing open-source chip design ecosystem from an environmental sustainability perspective
July 11, Tuesday (Day 2)
- 8:30-9:30, Early bird coffee and tea
Keynote speech
- 9:30-10:00, Luca Weiss (Fairphone), Open Source for Sustainable and Long lasting Phones
Hardware security
- 10:00-10:30, Jean Bruant (OVHcloud), Open-source electronic design automation for agile network defense at OVHcloud
- 10:30-11:00, Gaëtan Cassiers (TU Graz), Physical security for cryptographic implementations with open hardware
- 11:00-11:30, Pat Deegan (Psychogenic Technologies), Black-tie Python: Formal verification with Amaranth
- 11:30-12:00, Pablo Navarro (Seville Institute of Microelectronics), Exploring open hardware solutions for ensuring the security of RISC-V processors
- 12:00-13:30, lunch break
- 13:30-14:00, Gabriel Gouvine (LIP6), Logic Locking
- 14:00-14:30, Wei Cheng, Sylvain Guilley, and Olivier Rioul (Telecom Paris and Secure IC), All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)
IP blocks
- 14:30-15:00, Manuel Moser and Harald Pretl (Johannes Kepler University Linz), Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology
Transistor modelling and circuit simulation
- 15:00-15:30, Felix Salfelder (GnuCap), Verilog-AMS in Gnucap
Sustainability (part 2)
- 15:30-16:00, Maxime Pelcat (Univ Rennes, INSA Rennes and IETR), Environmental impacts of electronics and the role of open source hardware
- 16:00-16:30, Afternoon break. Coffee is served on-campus
- 16:30-17:00, Amael Parreaux-Ey (resilio), How to foster GreenIT through open hardware?
- 17:00-17:30, Julia Hess (Stiftung Neue Verantwortung), The importance of EU Academia in developing the chips of the future
- 17:30-18:00, Maurits Fennis (Unbinare), E-Waste Reverse Engineering Toolkit (RET)
Open-source standards and certifications
- 18:00-18:30, Martin Häuer (Open Source Ecology Germany e. V.), Standardizing Open Source Hardware, meet DIN SPEC 3105 – What has been done, what comes next and why this is awesome
Funding opportunities
- 18:30-19:00, Michiel Lenaars (NLnet Foundation), An overview of libre silicon and OSHW related efforts within NGI and NLnet
July 12, Wednesday (Day 3)
- 8:30-9:30, Early bird coffee and tea
Back-end design tools
- 9:30-10:00, Dan Fritchman (UC Berkeley), Open (and Closed) Source Analog Design with Hdl21 & VLSIR
- 10:00-10:30, Christophe Alexandre (Naja), Naja: project updates and netlist splitting tool
- 10:30-11:00, Pavel Smirnov (IQM), KQCircuits – open-source EDA software for designing chips with super conducting qubits
- 11:00-11:30, Jean-Paul Chaput (LIP6, Sorbonne Université), Coriolis a RTL to GDSII FOSS Design Flow
- 11:30-12:00, Matthias Köfferlein (KLayout), Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks
- 12:00-13:30, lunch break
Teaching and education
- 13:30-14:00, Martin Schoeberl (DTU Compute), Teaching Chip Design with Open-Source Tools
- 14:00-14:30, Gabriel Doriath Döhler and Constantin Gierczak-Galle (École normale supérieure), Learning hardware design in the video game Minecraft
- 14:30-15:00, Johan Euphrosine (Google), Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks
Paving the road for open source flow: gaps, challenges, opportunities
- 15:00-15:30, open discussion
- 15:30-16:00, conclusions
Physical location
4 Pl. Jussieu, 75005 Paris